/* * pciscc4.h: Header file for pciscc4.c - PCISCC-4 board driver * * Authors: Jens David * * CVS: $Id: pciscc4.h,v 1.21 2002/02/06 17:19:31 dg1kjd Exp $ * * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef _LINUX_PCISCC_H #define _LINUX_PCISCC_H #include #define PCISCC_MAGIC 0xbabe #ifdef __KERNEL__ /* General Registers */ #define GCMDR 0x0000 /* Global Command Register */ #define AR (1<<0) /* Action Request */ #define IMAR (1<<9) /* Interrupt Mask Action Request */ #define TXPR0 (1<<10) /* Transmit Poll Request Channel 0 */ #define TXPR1 (1<<11) /* Transmit Poll Request Channel 1 */ #define TXPR2 (1<<12) /* Transmit Poll Request Channel 2 */ #define TXPR3 (1<<13) /* Transmit Poll Request Channel 3 */ #define CFGIQP (1<<20) /* Configure IQ Peripheral */ #define CFGIQCFG (1<<21) /* Configure IQ Peripheral */ #define CFGIQSCC0TX (1<<24) /* Configure IQ SCC0 Transmit */ #define CFGIQSCC1TX (1<<25) /* Configure IQ SCC1 Transmit */ #define CFGIQSCC2TX (1<<26) /* Configure IQ SCC2 Transmit */ #define CFGIQSCC3TX (1<<27) /* Configure IQ SCC3 Transmit */ #define CFGIQSCC0RX (1<<28) /* Configure IQ SCC0 Receive */ #define CFGIQSCC1RX (1<<29) /* Configure IQ SCC1 Receive */ #define CFGIQSCC2RX (1<<30) /* Configure IQ SCC2 Receive */ #define CFGIQSCC3RX (1<<31) /* Configure IQ SCC3 Receive */ #define GSTAR 0x0004 /* Global Status Register */ #define ARACK (1<<0) /* Action Request Acknowledge Status */ #define ARF (1<<1) /* Action Request Failed Status */ #define IIPGPP (1<<16) /* Int. Indication Peripheral Queue GPP */ #define IIPLBI (1<<18) /* Int. Indication Peripheral Queue LBI */ #define IIPSSC (1<<19) /* Int. Indication Peripheral Queue SSC */ #define IICFG (1<<21) /* Int. Indication Configuration Queue */ #define IISCC0TX (1<<24) /* Int. Indication Queue SCC0 TX */ #define IISCC1TX (1<<25) /* Int. Indication Queue SCC1 TX */ #define IISCC2TX (1<<26) /* Int. Indication Queue SCC2 TX */ #define IISCC3TX (1<<27) /* Int. Indication Queue SCC3 TX */ #define IISCC0RX (1<<28) /* Int. Indication Queue SCC0 RX */ #define IISCC1RX (1<<29) /* Int. Indication Queue SCC1 RX */ #define IISCC2RX (1<<30) /* Int. Indication Queue SCC2 RX */ #define IISCC3RX (1<<31) /* Int. Indication Queue SCC3 RX */ #define GMODE 0x0008 /* Global Mode Register */ #define CMODE (1<<0) /* DMA Control Mode */ #define DBE (1<<1) /* DEMUX Burst Enable */ #define ENDIAN (1<<2) /* Endian Selection */ #define CHN (1<<13) /* Channel Number Highest Priority */ #define SPRI (1<<15) /* Select Priority */ #define PERCFG (1<<16) /* Peripheral Block Configuration */ #define LCD (1<<19) /* LBI Clock Division */ #define OSCPD (1<<21) /* Oscillator Power Down */ /* IRQ Queue Control Registers */ #define IQLENR1 0x000c /* Interrupt Queue Length Register 1 */ #define IQSCC0TXLEN (1<<12) /* Interrupt Queue SCC0 TX Length */ #define IQSCC1TXLEN (1<<8) /* Interrupt Queue SCC1 TX Length */ #define IQSCC2TXLEN (1<<4) /* Interrupt Queue SCC2 TX Length */ #define IQSCC3TXLEN (1<<0) /* Interrupt Queue SCC3 TX Length */ #define IQSCC0RXLEN (1<<28) /* Interrupt Queue SCC0 RX Length */ #define IQSCC1RXLEN (1<<24) /* Interrupt Queue SCC1 RX Length */ #define IQSCC2RXLEN (1<<20) /* Interrupt Queue SCC2 RX Length */ #define IQSCC3RXLEN (1<<16) /* Interrupt Queue SCC3 RX Length */ #define IQLENR2 0x0010 /* Interrupt Queue Length Register 2 */ #define IQPLEN (1<<16) /* Interrupt Queue Peripheral Length */ #define IQCFGLEN (1<<20) /* Interrupt Queue Configuration Length */ #define IQSCC0RXBAR 0x0014 /* Interrupt Queue SCC0 RX Base Address */ #define IQSCC1RXBAR 0x0018 /* Interrupt Queue SCC1 RX Base Address */ #define IQSCC2RXBAR 0x001c /* Interrupt Queue SCC2 RX Base Address */ #define IQSCC3RXBAR 0x0020 /* Interrupt Queue SCC3 RX Base Address */ #define IQSCC0TXBAR 0x0024 /* Interrupt Queue SCC0 TX Base Address */ #define IQSCC1TXBAR 0x0028 /* Interrupt Queue SCC1 TX Base Address */ #define IQSCC2TXBAR 0x002c /* Interrupt Queue SCC2 TX Base Address */ #define IQSCC3TXBAR 0x0030 /* Interrupt Queue SCC3 TX Base Address */ #define FIFOCR4 0x0034 /* FIFO Control Register 4 */ #define TFFTHRES0 (1<<0) /* Transmit FIFO Forward Threshold Chan. 0 */ #define TFFTHRES1 (1<<8) /* Transmit FIFO Forward Threshold Chan. 1 */ #define TFFTHRES2 (1<<16) /* Transmit FIFO Forward Threshold Chan. 2 */ #define TFFTHRES3 (1<<24) /* Transmit FIFO Forward Threshold Chan. 3 */ #define IQCFGBAR 0x003c /* CFG Interrupt Queue Base Address */ #define IQPBAR 0x0040 /* PER Interrupt Queue Base Address */ /* DMAC control registers */ #define FIFOCR1 0x0044 /* FIFO Control Register 1 */ #define TFSIZE0 (1<<27) /* Transmit FIFO Size Channel 0 */ #define TFSIZE1 (1<<22) /* Transmit FIFO Size Channel 1 */ #define TFSIZE2 (1<<17) /* Transmit FIFO Size Channel 2 */ #define TFSIZE3 (1<<11) /* Transmit FIFO Size Channel 3 */ #define FIFOCR2 0x0048 /* FIFO Control Register 2 */ #define M4_0 (1<<7) /* Multiplier 4 FIFO Channel 0 */ #define M2_0 (1<<6) /* Multiplier 2 FIFO Channel 0 */ #define M4_1 (1<<5) /* Multiplier 4 FIFO Channel 1 */ #define M2_1 (1<<4) /* Multiplier 2 FIFO Channel 1 */ #define M4_2 (1<<3) /* Multiplier 4 FIFO Channel 2 */ #define M2_2 (1<<2) /* Multiplier 2 FIFO Channel 2 */ #define M4_3 (1<<1) /* Multiplier 4 FIFO Channel 3 */ #define M2_3 (1<<0) /* Multiplier 2 FIFO Channel 3 */ #define TFRTHRES0 (1<<27) /* Transmit FIFO Refill Threshold Chan. 0 */ #define TFRTHRES1 (1<<22) /* Transmit FIFO Refill Threshold Chan. 1 */ #define TFRTHRES2 (1<<17) /* Transmit FIFO Refill Threshold Chan. 2 */ #define TFRTHRES3 (1<<11) /* Transmit FIFO Refill Threshold Chan. 3 */ #define FIFOCR3 0x004c /* FIFO Control Register 3 */ #define RFTHRES (1<<0) /* RX FIFO Threshold */ #define M2 (1<<7) /* RX FIFO Threshold Multiplier 2 */ #define M4 (1<<8) /* RX FIFO Threshold Multiplier 4 */ #define CH0CFG 0x0050 /* Channel 0 Configuration */ #define CH0BRDA 0x0054 /* Channel 0 Base Address RX Descriptor */ #define CH0BTDA 0x0058 /* Channel 0 Base Address TX Descriptor */ #define CH1CFG 0x005c /* Channel 1 Configuration */ #define CH1BRDA 0x0060 /* Channel 1 Base Address RX Descriptor */ #define CH1BTDA 0x0064 /* Channel 1 Base Address TX Descriptor */ #define CH2CFG 0x0068 /* Channel 2 Configuration */ #define CH2BRDA 0x006c /* Channel 2 Base Address RX Descriptor */ #define CH2BTDA 0x0070 /* Channel 2 Base Address TX Descriptor */ #define CH3CFG 0x0074 /* Channel 3 Configuration */ #define CH3BRDA 0x0078 /* Channel 3 Base Address RX Descriptor */ #define CH3BTDA 0x007c /* Channel 3 Base Address TX Descriptor */ #define IDT (1<<19) #define IDR (1<<20) #define RDT (1<<21) #define RDR (1<<22) #define MTERR (1<<24) /* Mask TX ERR-Interrupt */ #define MRERR (1<<25) /* Mask RX ERR-Interrupt */ #define MTFI (1<<26) /* Mask RX FI-Interrupt */ #define MRFI (1<<27) /* Mask TX FI-Interrupt */ #define CH0FRDA 0x0098 /* Channel 0 First RX Descriptor Address */ #define CH1FRDA 0x009c /* Channel 1 First RX Descriptor Address */ #define CH2FRDA 0x00a0 /* Channel 2 First RX Descriptor Address */ #define CH3FRDA 0x00a4 /* Channel 3 First RX Descriptor Address */ #define CH0FTDA 0x00b0 /* Channel 0 First TX Descriptor Address */ #define CH1FTDA 0x00b4 /* Channel 1 First TX Descriptor Address */ #define CH2FTDA 0x00b8 /* Channel 2 First TX Descriptor Address */ #define CH3FTDA 0x00bc /* Channel 3 First TX Descriptor Address */ #define CH0LRDA 0x00c8 /* Channel 0 Last RX Descriptor Address */ #define CH1LRDA 0x00cc /* Channel 1 Last RX Descriptor Address */ #define CH2LRDA 0x00d0 /* Channel 2 Last RX Descriptor Address */ #define CH3LRDA 0x00d4 /* Channel 3 Last RX Descriptor Address */ #define CH0LTDA 0x00e0 /* Channel 0 Last TX Descriptor Address */ #define CH1LTDA 0x00e4 /* Channel 1 Last TX Descriptor Address */ #define CH2LTDA 0x00e8 /* Channel 2 Last TX Descriptor Address */ #define CH3LTDA 0x00ec /* Channel 3 Last TX Descriptor Address */ /* SCC base addresses */ const long SCCBASE[] = {0x0100, 0x0180, 0x0200, 0x0280}; /* SCC registers */ #define CMDR 0x0000 /* Command Register */ #define RNR (1<<0) /* Receiver Not Ready Command */ #define STI (1<<8) /* Start Timer Command */ #define RRES (1<<16) /* Receiver Reset Command */ #define RFRD (1<<17) /* Receive FIFO Read Enable Command */ #define HUNT (1<<18) /* Enter Hunt State Command */ #define XRES (1<<24) /* Transmitter Reset Command */ #define STAR 0x0004 /* Status Register */ #define RRNR (1<<16) /* Received RNR Status */ #define XRNR (1<<17) /* Transmit RNR Status */ #define WFA (1<<18) /* Wait For Acknowledgement */ #define DPLA (1<<19) /* DPLL Asynchronous */ #define RLI (1<<20) /* Receive Line Inactive */ #define CD (1<<21) /* Carrier Detect Input Signal State */ #define RFNE (1<<22) /* Receive FIFO Not Empty */ #define SYNC (1<<23) /* Synchronisation Status */ #define CTS (1<<24) /* Clear To Send Input Signal State */ #define FCS (1<<27) /* Flow Control Status */ #define CEC (1<<28) /* Command Executing */ #define TEC (1<<29) /* TIC executing */ #define CCR0 0x0008 /* Channel Configuration Register 0 */ #define CM (1<<0) /* Clock Mode */ #define CM0 (1<<0) #define CM1 (1<<1) #define CM2 (1<<2) #define HS (1<<3) /* High Speed (PEB-20534H-52) */ #define SSEL (1<<4) /* Clock Source Select (a/b Select) */ #define TOE (1<<5) /* Transmit Clock Out Enable */ #define BCR (1<<7) /* Bit Clock Rate */ #define PSD (1<<8) /* DPLL Phase Shift Disable */ #define VIS (1<<12) /* Masked Interrupts Visible */ #define SM (1<<16) /* Serial Port Mode */ #define SM0 (1<<16) #define SM1 (1<<17) #define SC (1<<20) /* Serial Port Configuration */ #define SC0 (1<<20) #define SC1 (1<<21) #define SC2 (1<<22) #define PU (1<<31) /* Power Up */ #define CCR1 0x000c /* Channel Configuration Register 1 */ #define C32 (1<<0) /* CRC-32 Select */ #define TOLEN (1<<0) /* Time Out Length */ #define CRL (1<<1) /* CRC Reset Value */ #define SFLAG (1<<7) /* Shared Flags Transmission */ #define TOIE (1<<7) /* Time Out Indication Enable */ #define TLP (1<<8) /* Test Loop */ #define MCS (1<<9) /* Modulo Count Select */ #define PPM0 (1<<10) /* PPP Mode Select 0 */ #define BISNC (1<<10) /* Enable BISYNC Mode */ #define PPM1 (1<<11) /* PPP Mode Select 1 */ #define SLEN (1<<11) /* SYNC Character Length */ #define NRM (1<<12) /* Normal Response Mode */ #define ADM (1<<13) /* Address Mode Select */ #define MDS0 (1<<14) /* Mode Select (HDLC Protocol Sub-Mode) */ #define MDS1 (1<<15) #define CAS (1<<17) /* Carrier Detect Auto Start */ #define FCTS (1<<18) /* Flow Control (Using Signal /CTS) */ #define FRTS (1<<19) /* Flow Control (Using Signal /RTS) */ #define RTS (1<<20) /* Request To Send Pin Control */ #define TCLKO (1<<21) /* Transmit Clock Output */ #define ICD (1<<22) /* Invert Carrier Detect Pin Polarity */ #define ODS (1<<25) /* Output Driver Select */ #define DIV (1<<26) /* Data Inversion */ #define SOC0 (1<<28) /* Serial Output Control */ #define SOC1 (1<<29) #define CCR2 0x0010 /* Channel Configuration Register 2 */ #define XCRC (1<<0) /* Transmit CRC Checking Mode */ #define FLON (1<<0) /* Flow Control Enable */ #define CRCM (1<<0) /* CRC Mode Select */ #define OIN (1<<1) /* One Insertion */ #define CAPP (1<<1) /* CRC Append */ #define SXIF (1<<2) /* Selects Transmission Of I-Frames */ #define CRLBS (1<<2) /* CRC Reset Value In BISYNC Mode */ #define ITF (1<<3) /* Interframe Time Fill */ #define PRE0 (1<<4) /* Number Of Preamble Repetitions */ #define PRE1 (1<<5) #define EPT (1<<7) /* Enable Preamble Transmission */ #define PRE (1<<8) /* Preamble */ #define RFTH (1<<16) /* Receive FIFO Threshold */ #define RFDF (1<<19) /* Receive FIFO Data Format */ #define RADD (1<<20) /* Receive Address Pushed To FIFO */ #define DPS (1<<20) /* Data Parity Storage */ #define RCRC (1<<21) /* Receive CRC Checking Mode */ #define PARE (1<<21) /* Parity Enable */ #define DRCRC (1<<22) /* Disable Receive CRC Checking */ #define PAR0 (1<<22) /* Parity Format */ #define PAR1 (1<<23) #define STOP (1<<24) /* Stop Bit Number */ #define SLOAD (1<<24) /* Enable SYNC Character Load */ #define XBRK (1<<25) /* Transmit Break */ #define DXS (1<<26) /* Disable Storage of XON/XOFF-Characters */ #define RAC (1<<27) /* Receiver Active */ #define CHL0 (1<<28) /* Character Length */ #define CHL1 (1<<29) #define ACCM 0x0014 /* ASYNC Control Character Map */ #define UDAC 0x0018 /* User Defined ASYNC Character */ #define AC0 (1<<0) /* User Defined ASYNC Character Control Map */ #define AC1 (1<<8) /* User Defined ASYNC Character Control Map */ #define AC2 (1<<16) /* User Defined ASYNC Character Control Map */ #define AC3 (1<<24) /* User Defined ASYNC Character Control Map */ #define TTSA 0x001c /* TX Time Slot Assignment Register */ #define TCC (1<<0) /* Transmit Channel Capacity */ #define TEPCM (1<<15) /* Enable PCM Mask Transmit */ #define TCS (1<<16) /* Transmit Clock Shift */ #define TTSN (1<<24) /* Transmit Time Slot Number */ #define RTSA 0x0020 /* RX Time Slot Assignment Register */ #define RCC (1<<0) /* Receive Channel Capacity */ #define REPCM (1<<15) /* Enable PCM Mask Receive */ #define RCS (1<<16) /* Receive Clock Shift */ #define RTSN (1<<24) /* Receive Time Slot Number */ #define PCMMTX 0x0024 /* PCM Mask for Transmit */ #define PCMMRX 0x0028 /* PCM Mask for Receive */ #define BRR 0x002c /* Baud Rate Register */ #define BRN (1<<0) /* Baud Rate Factor N */ #define BRM (1<<8) /* Baud Rate Factor M k=(N+1)*2^M */ #define TIMR 0x0030 /* Timer Register */ #define TVALUE (1<<0) /* Timer Expiration Value */ #define CNT (1<<24) /* Counter */ #define TMD (1<<28) /* Timer Mode */ #define SRC (1<<31) /* Clock Source */ #define XADR 0x0034 /* TX Address Register */ #define XAD1 (1<<0) /* Transmit Address 1 */ #define XAD2 (1<<8) /* Transmit Address 2 */ #define RADR 0x0038 /* RX Address Register */ #define RAL1 (1<<16) /* RX Address 1 Low-Byte */ #define RAH1 (1<<24) /* RX Address 1 High-Byte */ #define RAL2 (1<<0) /* RX Address 2 Low-Byte */ #define RAH2 (1<<8) /* RX Address 2 High-Byte */ #define RAMR 0x003c /* Receive Address Mask Register */ #define AMRAL1 (1<<0) /* Receive Mask Address 1 Low-Byte */ #define AMRAH1 (1<<8) /* Receive Mask Address 1 High-Byte */ #define AMRAL2 (1<<16) /* Receive Mask Address 2 Low-Byte */ #define AMRAH2 (1<<24) /* Receive Mask Address 2 High-Byte */ #define RLCR 0x0040 /* Receive Length Check Register */ #define RL (1<<0) /* Receive Length Check Limit */ #define RCE (1<<15) /* Receive Length Check Enable */ #define XNXFR 0x0044 /* XON/XOFF Register */ #define MXOFF (1<<0) /* XOFF Character Mask */ #define MXON (1<<8) /* XON Character Mask */ #define CXOFF (1<<16) /* XOFF Character */ #define CXON (1<<24) /* XON Character */ #define TCR 0x0048 /* Termination Character Register */ #define TC (1<<0) /* Termination Character */ #define TCDE (1<<15) /* Termination Character Detection Enable */ #define TICR 0x004c /* Transmit Immediate Character Register */ #define SYNCR 0x0050 /* Synchronization Character Register */ #define SYNCL (1<<0) /* Synchronization Character Low */ #define SYNCH (1<<8) /* Synchronization Character High */ #define IMR 0x0054 /* Interrupt Mask Register */ #define ISR 0x0058 /* Interrupt Status Register */ #define FLEX (1<<0) /* Frame Length Exceeded Interrupt */ #define RFO (1<<1) /* RX FIFO Overflow Interrupt */ #define CDSC (1<<2) /* Carrier Detect Status Change Interrupt */ #define PLLA (1<<3) /* DPLL Asynchronous Interrupt */ #define PCE (1<<4) /* Protocol Error Interrupt */ #define FERR (1<<4) /* Framing Error Interrupt */ #define SCD (1<<4) /* SYN Character Detected Interrupt */ #define RSC (1<<5) /* Receive Status Change Interrupt */ #define PERR (1<<5) /* Parity Error Interrupt */ #define RFS (1<<6) /* Receive Frame Start Interrupt */ #define TIME (1<<6) /* Time Out Interrupt */ #define RDO (1<<7) /* Receive Data Overflow Interrupt */ #define TCD (1<<7) /* Termination Character Detected Interrupt */ #define BRKT (1<<8) /* Break Terminated Interrupt */ #define BRK (1<<9) /* Break Interrupt */ #define XPR (1<<12) /* Transmit Pool Ready Interrupt */ #define XMR (1<<13) /* Transmit Message Repeat */ #define XON (1<<13) /* XOFF Character Detected Interrupt */ #define CSC (1<<14) /* /CTS Status Change */ #define TIN (1<<15) /* Timer Interrupt */ #define XDU (1<<16) /* Transmit Data Underrun Interrupt */ #define ALLS (1<<18) /* All Sent Interrupt */ /* Peripheral control registers */ #define LCONF 0x0300 /* LBI Configuration Register */ #define MCTC (1<<0) /* LBI Memory Cycle Time Control */ #define ABM (1<<4) /* LBI Arbitration Master */ #define RDEN (1<<5) /* LBI LRDY Enable */ #define BTYP (1<<6) /* LBI Bus Type */ #define BTYP0 (1<<6) #define BTYP1 (1<<7) #define HDEN (1<<8) /* LBI HOLD Enable */ #define EALE (1<<9) /* LBI Extended ALE */ #define EBCRES (1<<22) /* LBI External Bus Controller Reset */ #define LINTIC (1<<31) /* LBI Interrupt Input Control */ #define SSCCON 0x0380 /* SSC Control Register */ #define SSCBM (1<<0) /* SSC Data Width Control */ #define SSCBC (1<<0) /* SSC Shift Counter */ #define SSCHB (1<<4) /* SSC Heading (Bit Order) Control */ #define SSCPH (1<<5) /* SSC Clock Phase Control */ #define SSCPO (1<<6) /* SSC Polarity Control */ #define SSCTEN (1<<8) /* SSC Transmit Error Enable */ #define SSCTE (1<<8) /* SSC Transmit Status Flag */ #define SSCREN (1<<9) /* SSC Receive Error Enable */ #define SSCRE (1<<9) /* SSC Receive Status Flag */ #define SSCPEN (1<<10) /* SSC Phase Error Enable */ #define SSCPE (1<<10) /* SSC Baud Rate Status Flag */ #define SSCBEN (1<<11) /* SSC Baud Rate Error Enable */ #define SSCBE (1<<11) /* SSC Baud Rate Status Flag */ #define SSCBSY (1<<12) /* SSC Busy Flag */ #define SSCMS (1<<14) /* SSC Master Select */ #define SSCEN (1<<15) /* SSC Enable */ #define SSCBR 0x0384 /* SSC Baud Rate Generator Register */ #define SSCTB 0x0388 /* SSC Transmit Buffer */ #define SSCRB 0x038c /* SSC Receive Buffer */ #define SSCCSE 0x0390 /* SSC Chip Select Enable Register */ #define ASEL0 (1<<4) /* SSC Chipselect 0 */ #define ASEL1 (1<<5) /* SSC Chipselect 1 */ #define ASEL2 (1<<6) /* SSC Chipselect 2 */ #define ASEL3 (1<<7) /* SSC Chipselect 3 */ #define SSCIM 0x0394 /* SSC Interrupt Mask Register */ #define IMTX (1<<0) /* SSC Transmit Interrupt Mask */ #define IMER (1<<1) /* SSC Error Interrupt Mask */ #define IMRX (1<<2) /* SSC Receive Interrupt Mask */ #define GPDIR 0x0400 /* GPP Direction Configuration Register */ #define GPDATA 0x0404 /* GPP Data I/O Register */ #define GPIM 0x0408 /* GPP Interrupt Mask Register */ /* Receive Data Section Status Byte (HDLC mode) */ #define SB_LA (1<<0) /* low byte address compare */ #define SB_CR (1<<1) /* command/response */ #define SB_HA0 (1<<2) /* high byte address compare */ #define SB_HA1 (1<<3) #define SB_RAB (1<<4) /* receive message aborted */ #define SB_CRC (1<<5) /* CRC compare */ #define SB_RDO (1<<6) /* receive data overflow */ #define SB_VFR (1<<7) /* valid frame */ /* Configuration Interrupt Vector */ #define CIV_ARACK (1<<0) /* action request acknowledge */ #define CIV_ARF (1<<1) /* action request failed */ #define CIV_SRCID (1<<28) /* source ID, always 0x0a */ #define CIV_SRCIDVAL 0x0a /* DMA Controller Interrupt Vector */ #define DMACIV_ERR (1<<16) /* error indication interrupt */ #define DMACIV_FI (1<<17) /* frame indication interrupt */ #define DMACIV_HI (1<<18) /* host initiated interrupt */ #define DMACIV_SRCID (1<<28) /* SCC Interrupt Vector */ #define SCCIV_FLEX (1<<0) /* Frame Length Exceeded Interrupt */ #define SCCIV_RFO (1<<1) /* RX FIFO Overflow Interrupt */ #define SCCIV_CDSC (1<<2) /* Carrier Detect Status Change Interrupt */ #define SCCIV_PLLA (1<<3) /* DPLL Asynchronous Interrupt */ #define SCCIV_PCE (1<<4) /* Protocol Error Interrupt */ #define SCCIV_FERR (1<<4) /* Framing Error Interrupt */ #define SCCIV_SCD (1<<4) /* SYN Character Detected Interrupt */ #define SCCIV_RSC (1<<5) /* Receive Status Change Interrupt */ #define SCCIV_PERR (1<<5) /* Parity Error Interrupt */ #define SCCIV_RFS (1<<6) /* Receive Frame Start Interrupt */ #define SCCIV_TIME (1<<6) /* Time Out Interrupt */ #define SCCIV_RDO (1<<7) /* Receive Data Overflow Interrupt */ #define SCCIV_TCD (1<<7) /* Termination Character Detected Interrupt */ #define SCCIV_BRKT (1<<8) /* Break Terminated Interrupt */ #define SCCIV_BRK (1<<9) /* Break Interrupt */ #define SCCIV_XPR (1<<12) /* Transmit Pool Ready Interrupt */ #define SCCIV_XMR (1<<13) /* Transmit Message Repeat */ #define SCCIV_XOFF (1<<13) /* XOFF Character Detected Interrupt */ #define SCCIV_CSC (1<<14) /* /CTS Status Change */ #define SCCIV_TIN (1<<15) /* Timer Interrupt */ #define SCCIV_XDU (1<<16) /* Transmit Data Underrun Interrupt */ #define SCCIV_ALLS (1<<18) /* All Sent Interrupt */ #define SCCIV_SRCID (1<<28) #define SCCIV_SCC (1<<25) /* 1: SCC generated. 0: DMAC generated */ #define SCCIV_ERR (1<<16) /* ERROR Indication Interrupt */ #define SCCIV_FI (1<<17) /* Frame Indication Interrupt */ #define SCCIV_HI (1<<18) /* Host Initiated Interrupt */ #define SCCIV_IGNORE (1<<20) /* internal use */ /* SSC Interrupt Vector */ #define SSCIV_INSW (1<<0) /* interrupt status word */ #define SSCIV_TX (1<<16) /* transmit interrupt */ #define SSCIV_RX (1<<17) /* receive interrupt */ #define SSCIV_ERR (1<<18) /* error interrupt */ #define SSCIV_DE (1<<23) /* data/error indication */ #define SSCIV_RT (1<<24) /* rx/tx indicator */ #define SSCIV_SRCID (1<<28) #define SSCIV_SRCIDVAL 0x0c /* LBI Interrupt Vector */ #define LBIIV_SRCID (1<<28) #define LBIIV_SRCIDVAL 0x0d /* GPP Interrupt Vector */ #define GPPIV_GPDATA (1<<0) #define GPPIV_SRCID (1<<28) #define GPPIV_SRCIDVAL 0x0f #endif /* __KERNEL__ */ /* Structure definitions */ struct devcfg_t { int coding; /* channel coding */ #define CFG_CHCODE_NONE 0 #define CFG_CHCODE_NRZ 1 /* non-return-to-zero */ #define CFG_CHCODE_NRZI 2 /* non-return-to-zero inverted */ #define CFG_CHCODE_FM0 3 /* FM-0 */ #define CFG_CHCODE_FM1 4 /* FM-1 */ #define CFG_CHCODE_MANCH 5 /* Manchester */ #define CFG_CHCODE_MIN 1 #define CFG_CHCODE_MAX 5 int clockmode; #define CFG_CM_NONE 0 #define CFG_CM_DF9IC 1 /* TXCLK, RXCLK external source */ #define CFG_CM_G3RUH 2 /* TXCLK generated by BRG intern */ #define CFG_CM_TCM3105 3 /* TXCLK from BRG, RXCLK from DPLL */ #define CFG_CM_HS 4 /* high-Speed mode */ #define CFG_CM_MIN 1 #define CFG_CM_MAX 4 int duplex; /* duplex mode */ #define CFG_DUPLEX_HALF 0 #define CFG_DUPLEX_FULL 1 #define CFG_DUPLEX_FULLPTT 2 /* full duplex with PTT always asserted */ #define CFG_DUPLEX_MIN 0 #define CFG_DUPLEX_MAX 2 int dpll; /* DPLL configuration */ #define CFG_DPLL_PS (1<<0) /* 180 deg phase shift enable */ int brate_m; /* BRG "M" */ #define CFG_BRATEM_MAX 15 int brate_n; /* BRG "N" */ #define CFG_BRATEN_MAX 63 int clkout; /* enable clock out */ #define CFG_TXTXCLK (1<<0) /* tx-clock on TXCLK */ #define CFG_TXRTS (1<<1) /* tx-clock on RTS in highspeed mode */ int datainv; /* NRZ data inversion */ int txddrive; /* TXD driver select */ #define CFG_TXDDRIVE_NONE 0 #define CFG_TXDDRIVE_TP 1 /* totem pole */ #define CFG_TXDDRIVE_OD 2 /* open drain */ #define CFG_TXDDRIVE_MIN 1 #define CFG_TXDDRIVE_MAX 2 int cdinv; /* CD line invert */ int testloop; /* TXD<->RXD testloop */ int txdelmode; /* TX-delay mode */ #define CFG_TXDEL_NONE 0 #define CFG_TXDEL_SOFT 1 /* TX-delay software generated */ #define CFG_TXDEL_HARD 2 /* TX-delay generated by modem (CTS) */ #define CFG_TXDEL_MIN 1 #define CFG_TXDEL_MAX 2 int txdelval; /* txdelay value */ int txtailval; /* txtail value */ int sharedflg; /* use shared flags */ int crcmode; /* CRC check */ #define CFG_CRCMODE_CRC32 (1<<0) /* 1: CRC-32 0:CRC-16 */ #define CFG_CRCMODE_RESET_0000 (1<<1) /* 1: reset value 0x0000 0: 0xFFFF */ #define CFG_CRCMODE_RXCD (1<<2) /* 1: disable RX CRC check 0: enable */ #define CFG_CRCMODE_RXCRCFWD (1<<3) /* 1: forward crc bytes 0: dont */ #define CFG_CRCMODE_TXNOCRC (1<<4) /* 0: generate and append CRC 1: dont */ int preamb_rpt; /* number of preamble repeats 0=off */ unsigned char preamble; /* preamble value */ int hdlcext; /* HDLC extensions */ #define CFG_HDLCEXT_ONEINS (1<<0) /* one insertion after seven zeros */ #define CFG_HDLCEXT_ONEFILL (1<<1) /* 1: interframe fill by ones 0: flags */ }; struct chipcfg_t { unsigned long lbimode; /* local bus mode 1:1 reg */ int oscpwr; /* oscillator power */ int rxbufcnt; /* number of RX descriptors and buffers */ int txbufcnt; /* number of TX descriptors */ int iqlen; /* irq-queuelen */ int prichan; /* priority channel -1=none */ int mfifo_rx_t; /* RX main-FIFO DMA init threshold dwords */ }; #ifdef __KERNEL__ #include struct devctl_t { struct device dev; /* link to netdev struct */ struct ax25_dev ax25dev; struct chipctl_t *chip; struct devcfg_t cfg; int channel; /* channel number */ char name[10]; unsigned long * volatile iq_rx; /* interrupt queues */ unsigned long * volatile iq_tx; unsigned long * volatile iq_rx_next; /* next entry to be processed */ unsigned long * volatile iq_tx_next; struct rx_desc_t * volatile dq_rx; /* RX descriptor queue */ struct rx_desc_t * volatile dq_rx_next; struct tx_desc_t * volatile dq_tx; /* TX descriptor queue */ struct tx_desc_t * volatile dq_tx_cleanup; /* first to be cleaned up after transmission */ struct tx_desc_t * volatile dq_tx_last; /* last one to be transmitted */ volatile unsigned long rx_mailbox; /* communication with isr */ volatile unsigned long tx_mailbox; /* communication with isr */ volatile unsigned long probe_mailbox; /* communication with isr */ struct net_device_stats stats; /* statistics */ volatile int txstate; unsigned long last_tx; /* jiffy-timestamp of last TX frame queued (for tbusy) */ unsigned long ccr0, ccr1, ccr2; /* SCC control register 0:2 save */ int dmac_rx; /* DMA controller RX state */ #define DMAC_RX_RESET 0 /* RESET state */ #define DMAC_RX_INIT 1 /* initialized */ volatile long tx_bitrate; /* effective TX bitrate, probed if extern */ struct timeval tv; /* for baudrate probe */ spinlock_t dev_lock; /* spinlock for device */ }; struct chipctl_t { struct pci_dev *pcidev; struct chipcfg_t cfg; struct devctl_t *device[4]; unsigned long * volatile iq_per; /* peripheral interrupt queue */ unsigned long * volatile iq_cfg; /* configuration interrupt queue */ unsigned long * volatile iq_per_next; /* next entry to be processed */ unsigned long * volatile iq_cfg_next; void *io_base; void *lbi_base; unsigned int irq; int initialized; /* chip initialized? */ int usecnt; /* number of open channels on chip */ volatile unsigned long mailbox; /* communication with isr */ #define MAILBOX_NONE 0 #define MAILBOX_OK 1 #define MAILBOX_FAILURE 2 spinlock_t chip_lock; /* spinlock for chip */ }; struct tx_desc_t { volatile long flags __attribute__ ((packed)); #define NO (1<<16) /* number of bytes */ #define HI (1<<29) /* host initiated interrupt */ #define HOLD (1<<30) /* last descriptor in chain */ #define FE (1<<31) /* frame end */ volatile void * volatile nextptr __attribute__ ((packed)); /* note busaddr */ volatile void * volatile dataptr __attribute__ ((packed)); volatile unsigned long result __attribute__ ((packed)); #define C (1<<30) /* descriptor complete flag */ struct sk_buff *skb; /* pointer to complete sk_buff */ struct tx_desc_t *next; /* note virtaddr */ struct tx_desc_t *prev; }; struct rx_desc_t { volatile long flags __attribute__ ((packed)); #define RA (1<<9) /* receive abort */ #define BNO (1<<16) /* byte number of received data */ volatile void * volatile nextptr __attribute__ ((packed)); /* note busaddr */ volatile void * volatile dataptr __attribute__ ((packed)); volatile unsigned long result __attribute__ ((packed)); volatile struct rx_desc_t * volatile feptr __attribute__ ((packed)); struct sk_buff *skb; /* pointer to complete sk_buff */ struct rx_desc_t *next; /* note virtaddr */ struct rx_desc_t *prev; /* previous */ }; #define SKB_HEADROOM (AX25_MAX_HEADER_LEN + (4-(AX25_MAX_HEADER_LEN % 4))) /* keep dword alignment */ #endif /* __KERNEL__ */ /* ioctl()s */ #define SIOCPCISCCGCCFG SIOCDEVPRIVATE #define SIOCPCISCCSCCFG (SIOCDEVPRIVATE+1) #define SIOCPCISCCGDCFG (SIOCDEVPRIVATE+2) #define SIOCPCISCCSDCFG (SIOCDEVPRIVATE+3) #define SIOCPCISCCSLED (SIOCDEVPRIVATE+4) #define SIOCPCISCCGDSTAT (SIOCDEVPRIVATE+5) #define SIOCPCISCCDCAL (SIOCDEVPRIVATE+6) #define SIOCPCISCCLBI (SIOCDEVPRIVATE+7) #define SIOCPCISCCKICKTX (SIOCDEVPRIVATE+8) #define TX_MIN 0 #define TX_RESET 0 #define TX_IDLE 1 #define TX_DELAY 2 #define TX_XMIT 3 #define TX_TAIL 4 #define TX_PROBE 5 #define TX_CAL 6 #define TX_MAX 6 #define STATUS_DPLA (1<<4) #define STATUS_RLI (1<<5) #define STATUS_CD (1<<6) #define STATUS_CTS (1<<7) #define STATUS_RTS (1<<8) struct lbi_xfer { unsigned int mode; #define LBI_READ 0 #define LBI_WRITE 1 unsigned short addr; unsigned short data; }; #ifdef __KERNEL__ /* In pciscc4.c */ #ifdef PCISCC_DEBUG static void pciscc_dmac_regdump(struct chipctl_t *cctlp); static void pciscc_queuedump(struct devctl_t *dctlp); #endif static int pciscc_chip_open(struct chipctl_t *cctlp); static int pciscc_chip_close(struct chipctl_t *cctlp); static int pciscc_channel_open(struct devctl_t *dctlp); static void pciscc_channel_close(struct devctl_t *dctlp); static void pciscc_isr(int irq, void *dev_id, struct pt_regs *regs); static __inline__ void pciscc_isr_receiver(struct devctl_t *dctlp); static __inline__ int pciscc_isr_txcleanup(struct devctl_t *dctlp); static void pciscc_bh_txto(void *arg); static void pciscc_bh_txreset(void *arg); static __inline__ void pciscc_clear_timer(struct devctl_t *dctlp); static long pciscc_probe_txrate(struct devctl_t *dctlp); static __inline__ void pciscc_set_txstate(struct devctl_t *dctlp, int state); static void pciscc_setptt(struct device *dev); static unsigned int pciscc_getdcd(struct device *dev); static unsigned int pciscc_getcts(struct device *dev); static unsigned int pciscc_getptt(struct device *dev); static void pciscc_parameter_notify(struct device *dev, int valueno, int old, int new); static int pciscc_brg2rate(int m, int n); static void pciscc_rate2brg(int rate, int *m, int *n); static void pciscc_update_values(struct device *dev); static int pciscc_dev_close(struct device *dev); static int pciscc_dev_open(struct device *dev); static int pciscc_change_mtu(struct device *dev, int new_mtu); static struct net_device_stats * pciscc_get_stats(struct device *dev); static int pciscc_dev_init(struct device *devctl); static int pciscc_dev_set_mac_address(struct device *dev, void *addr); static int pciscc_dev_ioctl(struct device *dev, struct ifreq *rq, int cmd); static void pciscc_kick_tx(struct devctl_t *dctlp); static int pciscc_xmit(struct sk_buff *skb, struct device *dev); static __inline__ void pciscc_rx_skb(struct sk_buff *skb, struct devctl_t *dctlp); void cleanup_module(void); int init_module(void); #endif /* __KERNEL__ */ #endif /* _LINUX_PCISCC.H */